1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices and to a semiconductor device and, in particular, to a method of manufacturing heterojunction bipolar transistors having reproducible and repeatable device characteristics in a simplified manner while eliminating parasitic components.
2. Discussion of the Background
Heterojunction bipolar transistors are commonly manufactured having a vertical structure. Emitter, collector and base layers are deposited and emitter and collector mesas are formed from the respective layers. Alignment of the collector and emitter mesas is critical to device performance. Other manufacturing methods have attempted to produce vertical HBT devices with aligned emitter and collector regions. This a critical alignment and any manufacturing errors diminishes device performance. Further, these methods do not provide the necessary tolerance to produce a manufacturable HBT having reproducible and repeatable device characteristics necessary for a commercial device.
U.S. Pat. No. 5,318,916 describes a method of symmetric self aligned processing, the disclosure of which is herein incorporated by reference. Symmetric emitter and collector portions are formed using front and back side processing of a wafer. An emitter mesa is etched using an emitter contact or other feature as a mask on the front side of the wafer. The collector layer is formed using back side processing where the substrate is removed to expose the collector layer. A contact is formed on the collector layer symmetrically aligned with the emitter contact. This process is done photolithographically and may be misaligned due to manufacturing tolerances.
The collector layer is etched to produce the collector mesa. The alignment of the collector contact may be improved in the case of very thin layers with an infrared alignment tool. However, the alignment of the emitter and collector is still a critical alignment step and subject to manufacturing tolerances and misalignment. Any misalignment or offset due to the photolithographic or other processing steps will degrade the device characteristics and limit scaling of the device to a minimum feature size.
It is an object of the present invention is to provide a symmetric self-aligned manufacturing process and device having high reproducibility and repeatability.
Another object of the present invention to provide a method of manufacturing with high reproducibility and repeatability necessary for commercial manufacturing.
A further object of the present invention to provide a method whereby a symmetric intrinsic process can be realized to a scale of xcx9c0.1 xcexcm without requiring any critical alignment.
A still further object of the invention to form a collector in a heterojunction bipolar transistor on one side of a stack of epitaxial layers in a self-aligned and symmetric manner to an emitter on another side of a stack of epitaxial layers.
Still another object of the invention is to provide a device and a process to manufacture a device have a self-aligned and self-centered configuration.
These and other objects are achieved by a method of fabricating semiconductor device including steps of forming an emitter and a base region, and forming a collector region symmetrically self-aligned with the emitter region. The collector portion may be further formed to be self-centered with the base region. The emitter, base and collector regions may be formed from a plurality of layers which are etched to form a vertical structure where the emitter, base and collector regions have substantially the same width. The method may also include a step of etching the emitter region to form an emitter portion having a width less than a width of the emitter region and being self-centered with the base region or a step of etching the collector region to form a collector portion having a width less than a width of the collector region and being self-centered with the base region.
The method may also include processing the device from both the emitter side of the device and the collector side of the device. The emitter portion may be formed from the emitter side of the device and the collector portion may be formed from the collector side of the device. Further, the device may consist of a plurality of layers formed on the substrate. The emitter region may be formed using one of the layers using processing on a front side of the substrate, the collector region may be formed from one of the layers using processing on the front side of the substrate, and a contact to the collector region may be formed using processing from a back side of the substrate.
The method according to the invention may also include forming a removable material over the emitter layer and attaching a second substrate to the removable material. The substrate may be removed to expose the collector region.
The collector region may be etched to have a desired width less than a width of the base region and greater than a width of the emitter region.
The method may further include the steps of forming the emitter, base and collector regions on a first substrate, depositing a removable film over the regions, attaching a second substrate to the film and then removing the first substrate to expose the collector region. After removing the first substrate, the collector region may be etched to form a collector portion having a width less than a width of the base region and being self-centered with the base region. The collector may also be etched after removing the substrate to have a width less than a width of the base region and greater than a width of the emitter region.
In a second embodiment of the method according to the invention, an emitter mesa may be formed and a sidewall may be formed on the emitter mesa. The step of forming the sidewall may be repeated a desired number of times to form a thick sidewall on the emitter mesa, or a dummy emitter may be used to produce a sidewall of a desired thickness. The base region and the collector region may then be formed having substantially the same width using the thick sidewall as a mask. The emitter mesa is self-centered with the base region. The second embodiment may also include steps of forming the emitter, collector and base regions on a first substrate, depositing a removable film over the regions, attaching a second substrate to the film and removing the first substrate to expose the collector region.
The method according to the invention may also be used to form heterojunction bipolar transistor emitter, base and collector regions. The emitter region is symmetrically self-aligned to the collector region, the emitter region is self-centered to the base region and the collector region is self-centered to the base region.
The method according to the invention may also be used to form a semiconductor device from a plurality of stacked layers. A first active region may be formed from one of the layers, and a second active region separated from the first active region by a third active layer may be formed. The first and second active regions are formed to be symmetrically self-aligned with respect to each other and self-centered with respect to the third active region. Such devices may be static induction transistors or vertical heterojunction FETs.
In another use of the method according to the invention, a plurality of layers may be formed on a substrate including a collector layer, a base layer and an emitter layer. The method may include a step of symmetrically self-aligning the collector layer, base layer and a emitter layer using processing from only one side of the substrate. An emitter region may be formed from the emitter layer self-centered with respect to the base layer, and a collector region may be formed in a collector layer self-centered with respect to the base region. The collector region may be formed using processing from a front side of substrate and a contact to the collector region may be formed using processing from a back side of the substrate. Symmetrically self-aligning the collector, base layer and emitter layer may be performed using processing on a front side of the substrate. An narrower emitter portion may be formed in the emitter layer self-centered with respect to the base region using processing on the front side of the substrate, and a narrower collector portion may be formed in the collector layer self-centered with respect to the base region using processing from a back side of the substrate.
The above and other objects may also be achieved by a semiconductor device having a base, an emitter and a collector. The collector is symmetrically self-aligned with the emitter. The collector and the emitter may be further self-centered with the base. The emitter may have a narrow portion self-centered with the base and the collector portion may also have a narrow portion self-centered with the base and symmetric with the emitter portion. The base layer may have a lower ledge and an upper ledge. A first base contact may be formed on the upper ledge self-aligned with the emitter and a second base contact may be formed on the lower ledge self-aligned with the collector. The collector may have a width less than a width of the base and greater than a width of the emitter. Further, the device may be a heterojunction bipolar transistor.